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第12行： 第12行：
 
Conversely, the 4000-series has "borrowed" from the 7400 series{{snd}} such as the CD40193 and CD40161 being pin-for-pin ''functional'' replacements for 74C193 and 74C161.
 
Conversely, the 4000-series has "borrowed" from the 7400 series{{snd}} such as the CD40193 and CD40161 being pin-for-pin ''functional'' replacements for 74C193 and 74C161.
  
−
Older TTL parts made by manufacturers such as [[Signetics]], [[Motorola]], [[Mullard]] and [[Siemens]] may have different numeric prefix and numbering series entirely, such as in the European FJ family FJH101 is an 8输入 [[NAND gate]] like a 7430.
+
Older TTL parts made by manufacturers such as [[Signetics]], [[Motorola]], [[Mullard]] and [[Siemens]] may have different numeric prefix and numbering series entirely, such as in the European FJ family FJH101 is an 8输入 [[与非门]] like a 7430.
  
 
A few alphabetic characters to designate a specific [[7400-series integrated circuits#Families|logic subfamily]] may immediately follow the '''74''' or '''54''' in the part number, e.g., 74LS74 for low-power [[Schottky diode|Schottky]]. Some CMOS parts such as 74HCT74 for high-speed [[CMOS]] with TTL-compatible input thresholds are functionally similar to the TTL part. Not all functions are available in all families.
 
A few alphabetic characters to designate a specific [[7400-series integrated circuits#Families|logic subfamily]] may immediately follow the '''74''' or '''54''' in the part number, e.g., 74LS74 for low-power [[Schottky diode|Schottky]]. Some CMOS parts such as 74HCT74 for high-speed [[CMOS]] with TTL-compatible input thresholds are functionally similar to the TTL part. Not all functions are available in all families.
第104行： 第104行：
 
* SN54LS54 = single 2-3-3-2 AOI gate
 
* SN54LS54 = single 2-3-3-2 AOI gate
  
−
==Larger footprints==
+
==较多pin脚的芯片==
−
Parts in this section have a pin count of 14 pins or more.  The lower part numbers were established in the 1960s and 1970s, then higher part numbers were added incrementally over decades.  IC manufacturers continue to make a core subset of this group, but many of these part numbers are considered obsolete and no longer manufactured.  Older discontinued parts may be available from a limited number of sellers as [[new old stock]] (NOS), though some are much harder to find.
+
 
 +
本节中的器件的引脚数为14个及以上。较小芯片编号是在20世纪60年代和70年代发布的，然后几十年来逐步有更高的芯片编号。IC制造商继续制造那些广泛使用的芯片，而其他许多芯片编号被认为是过时的，并不再生产了。较旧的芯片型号可能从有限的卖家处获得，比如 [[new old stock]](NOS)即新的原始库存，尽管有些芯片型号更难找到。
 +
 
 +
 
 +
对于下表：
 +
* 芯片型号列{{snd}} "x"是 [[7400-series integrated circuits#Families|logic subfamily]] 的占位符. 例如，74x00芯片在“LS”逻辑系列中就是“74LS00”。
 +
* 描述列{{snd}} 包括术语施密特触发器、集电极开路/漏极开路、三态被移动到输入列和输出列，以便更容易地按这些特征进行排序。
 +
* 输入列{{snd}} 空白单元格表示正常输入。
 +
* 输出列{{snd}} 空白单元格表示"totem pole" 输出，也称为 [[push–pull output]]，能够驱动同一逻辑子类芯片的十个标准输入 ([[fan-out]] N<sub>O</sub>&nbsp;=&nbsp;10). 具有更高输出电流的芯片型号通常称为驱动器或缓冲器。
 +
* Pin数目列{{snd}} [[雙列直插封裝]] (DIP) 封装的pin脚数目; 括号（圆括号）中的数字表示该 IC 没有已知的双列直插式封装版本。
  
−
For the following table:
 
−
* Part number column{{snd}} the "x" is a place holder for the [[7400-series integrated circuits#Families|logic subfamily]] name. For example, 74x00 in "LS" logic family would be "74LS00".
 
−
* Description column{{snd}} the terms Schmitt trigger, open-collector/open-drain, three-state were moved to the input and output columns to make it easier to sort by those features.
 
−
* Input column{{snd}} a blank cell means a normal input for the logic family type.
 
−
* Output column{{snd}} a blank cell means a "totem pole" output, also known as a [[push–pull output]], with the ability to drive ten standard inputs of the same logic subfamily ([[fan-out]] N<sub>O</sub>&nbsp;=&nbsp;10). Outputs with higher output currents are often called drivers or buffers.
 
−
* Pins column{{snd}} number of pins for the [[2个 in-line package]] (DIP) version; a number in [[parentheses]] (round brackets) indicates that there is no known 2个 in-line package version of this IC.
 
  
 
{|class="wikitable sortable"
 
{|class="wikitable sortable"
第120行： 第123行：
 
| 74x00
 
| 74x00
 
| 4
 
| 4
−
| 4个 2输入 [[NAND gate]]
+
| 4个 2输入 [[与非门|NAND与非门]]
 
|
 
|
 
|
 
|
第1,221行： 第1,224行：
 
| 4个 bus buffer, negative enable
 
| 4个 bus buffer, negative enable
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 14
 
| 14
 
| [http://www.ti.com/lit/gpn/sn74ls126a SN74LS125A]
 
| [http://www.ti.com/lit/gpn/sn74ls126a SN74LS125A]
第1,229行： 第1,232行：
 
| 4个 bus buffer, positive enable
 
| 4个 bus buffer, positive enable
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 14
 
| 14
 
| [http://www.ti.com/lit/gpn/sn74ls126a SN74LS126A]
 
| [http://www.ti.com/lit/gpn/sn74ls126a SN74LS126A]
第1,285行： 第1,288行：
 
| 1个 12输入 NAND与非门
 
| 1个 12输入 NAND与非门
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn54s134 SN74S134]
 
| [http://www.ti.com/lit/gpn/sn54s134 SN74S134]
第1,589行： 第1,592行：
 
| 16-bit multiple port register file (8x2)
 
| 16-bit multiple port register file (8x2)
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 24
 
| 24
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n729 SN74172]
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n729 SN74172]
第1,597行： 第1,600行：
 
| 4个 D flip-flop, asynchronous clear
 
| 4个 D flip-flop, asynchronous clear
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn54ls173a SN74173]
 
| [http://www.ti.com/lit/gpn/sn54ls173a SN74173]
第1,725行： 第1,728行：
 
| 64-bit RAM (16x4), 4 data inputs, 4 inverted data outputs
 
| 64-bit RAM (16x4), 4 data inputs, 4 inverted data outputs
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n191 SN74S189]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n191 SN74S189]
第1,816行： 第1,819行：
 
| 256-bit RAM (256x1)
 
| 256-bit RAM (256x1)
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_nationaldaTTLDatabook_42712617/page/nal_TTL_Databook#page/n299 DM74S200]
 
| [https://archive.org/details/bitsavers_nationaldaTTLDatabook_42712617/page/nal_TTL_Databook#page/n299 DM74S200]
第1,824行： 第1,827行：
 
| 256-bit RAM (256x1)
 
| 256-bit RAM (256x1)
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n195 SN74S201]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n195 SN74S201]
第1,832行： 第1,835行：
 
| 256-bit RAM (256x1) with power down
 
| 256-bit RAM (256x1) with power down
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBook2ed05_2617547/page/n51 SN74LS202]
 
| [https://archive.org/details/bitsavers_tidataBook2ed05_2617547/page/n51 SN74LS202]
第1,848行： 第1,851行：
 
| 1024-bit RAM (256x4)
 
| 1024-bit RAM (256x4)
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n205 SN74LS207]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n205 SN74LS207]
第1,856行： 第1,859行：
 
| 1024-bit RAM (256x4), separate data in- and outputs
 
| 1024-bit RAM (256x4), separate data in- and outputs
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n205 SN74LS208]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n205 SN74LS208]
第1,864行： 第1,867行：
 
| 1024-bit RAM (1024x1)
 
| 1024-bit RAM (1024x1)
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookmoryDataBook1975_9924035/page/nductor_Memory_Data_Book_1975#page/n171 SN74S209]
 
| [https://archive.org/details/bitsavers_tidataBookmoryDataBook1975_9924035/page/nductor_Memory_Data_Book_1975#page/n171 SN74S209]
第1,872行： 第1,875行：
 
| 8个 buffer, inverting
 
| 8个 buffer, inverting
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n311 SN74LS210]
 
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n311 SN74LS210]
第1,880行： 第1,883行：
 
| 144-bit RAM (16x9) with output latch
 
| 144-bit RAM (16x9) with output latch
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n181 74F211]
 
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n181 74F211]
第1,888行： 第1,891行：
 
| 144-bit RAM (16x9)
 
| 144-bit RAM (16x9)
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n185 74F212]
 
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n185 74F212]
第1,896行： 第1,899行：
 
| 192-bit RAM (16x12)
 
| 192-bit RAM (16x12)
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n189 74F213]
 
| [https://archive.org/details/bitsavers_fairchilddldFASTDataBook_29981933/page/n189 74F213]
第1,904行： 第1,907行：
 
| 1024-bit RAM (1024x1)
 
| 1024-bit RAM (1024x1)
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n199 SN74LS214]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n199 SN74LS214]
第1,912行： 第1,915行：
 
| 1024-bit RAM (1024x1) with power-down mode
 
| 1024-bit RAM (1024x1) with power-down mode
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n199 SN74LS215]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n199 SN74LS215]
第1,920行： 第1,923行：
 
| 256-bit RAM (64x4), common I/O
 
| 256-bit RAM (64x4), common I/O
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0044696.pdf SN74LS216]
 
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0044696.pdf SN74LS216]
第1,928行： 第1,931行：
 
| 256-bit RAM (64x4)
 
| 256-bit RAM (64x4)
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n173 SN74ALS217]
 
| [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n173 SN74ALS217]
第1,936行： 第1,939行：
 
| 256-bit RAM (32x8)
 
| 256-bit RAM (32x8)
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n173 SN74ALS218]
 
| [https://archive.org/details/bitsavers_tidataBookuitsDataBook_32771470/page/n173 SN74ALS218]
第1,944行： 第1,947行：
 
| 64-bit RAM (16x4), non-inverting outputs
 
| 64-bit RAM (16x4), non-inverting outputs
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/stream/SupplementToTheTTLDataBookForDesignEngineers2ndEdition/Supplement%20to%20The%20TTL%20Data%20Book%20for%20Design%20Engineers_2nd_Edition#page/n5 SN74LS219]
 
| [https://archive.org/stream/SupplementToTheTTLDataBookForDesignEngineers2ndEdition/Supplement%20to%20The%20TTL%20Data%20Book%20for%20Design%20Engineers_2nd_Edition#page/n5 SN74LS219]
第1,960行： 第1,963行：
 
| 64-bit [[FIFO (computing and electronics)|FIFO]] memory (16x4), synchronous, input/output ready enable
 
| 64-bit [[FIFO (computing and electronics)|FIFO]] memory (16x4), synchronous, input/output ready enable
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [http://www.ralphselectronics.com/productimages/SEMI-SN74LS224N.PDF SN74LS222]
 
| [http://www.ralphselectronics.com/productimages/SEMI-SN74LS224N.PDF SN74LS222]
第1,968行： 第1,971行：
 
| 64-bit [[FIFO (computing and electronics)|FIFO]] memory (16x4), synchronous
 
| 64-bit [[FIFO (computing and electronics)|FIFO]] memory (16x4), synchronous
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [http://www.ralphselectronics.com/productimages/SEMI-SN74LS224N.PDF SN74LS224]
 
| [http://www.ralphselectronics.com/productimages/SEMI-SN74LS224N.PDF SN74LS224]
第1,976行： 第1,979行：
 
| 80-bit FIFO memory (16x5), asynchronous
 
| 80-bit FIFO memory (16x5), asynchronous
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [http://www.ti.com/lit/gpn/sn74s225 SN74S225]
 
| [http://www.ti.com/lit/gpn/sn74s225 SN74S225]
第1,984行： 第1,987行：
 
| 4-bit parallel latched bus transceiver
 
| 4-bit parallel latched bus transceiver
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n219 SN74S226]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n219 SN74S226]
第2,008行： 第2,011行：
 
| 80-bit FIFO memory (16x5), asynchronous
 
| 80-bit FIFO memory (16x5), asynchronous
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://web.archive.org/web/20070101063514/http://focus.ti.com/lit/ds/symlink/sn74als229b.pdf SN74ALS229B]
 
| [https://web.archive.org/web/20070101063514/http://focus.ti.com/lit/ds/symlink/sn74als229b.pdf SN74ALS229B]
第2,016行： 第2,019行：
 
| 2个 4-bit buffer/driver, one inverted, one non-inverted; negative enable
 
| 2个 4-bit buffer/driver, one inverted, one non-inverted; negative enable
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n245 SN74AS230]
 
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n245 SN74AS230]
第2,024行： 第2,027行：
 
| 2个 4-bit buffer/driver, both inverted; one positive and one negative enable
 
| 2个 4-bit buffer/driver, both inverted; one positive and one negative enable
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n245 SN74AS231]
 
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n245 SN74AS231]
第2,032行： 第2,035行：
 
| 64-bit FIFO memory (16x4), asynchronous
 
| 64-bit FIFO memory (16x4), asynchronous
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn74als232b SN74ALS232B]
 
| [http://www.ti.com/lit/gpn/sn74als232b SN74ALS232B]
第2,040行： 第2,043行：
 
| 80-bit FIFO memory (16x5), asynchronous
 
| 80-bit FIFO memory (16x5), asynchronous
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n101 SN74ALS233B]
 
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n101 SN74ALS233B]
第2,048行： 第2,051行：
 
| 256-bit FIFO memory (64x4), asynchronous
 
| 256-bit FIFO memory (64x4), asynchronous
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n63 SN74ALS234]
 
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n63 SN74ALS234]
第2,056行： 第2,059行：
 
| 320-bit FIFO memory (64x5), asynchronous
 
| 320-bit FIFO memory (64x5), asynchronous
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n109 SN74ALS235]
 
| [https://archive.org/details/bitsavers_tidataBookeFIFOMemoriesDatabook_63352841/page/nce_FIFO_Memories_Databook#page/n109 SN74ALS235]
第2,064行： 第2,067行：
 
| 256-bit FIFO memory (64x4), asynchronous
 
| 256-bit FIFO memory (64x4), asynchronous
 
|
 
|
−
| [[Three-state logic|three-state]]
+
| [[三态逻辑|三态逻辑]]
 
| 16
 
| 16
 
| [https://web.archive.org/web/20070102044700/http://focus.ti.com/lit/ds/symlink/sn74als236.pdf SN74ALS236]
 
| [https://web.archive.org/web/20070102044700/http://focus.ti.com/lit/ds/symlink/sn74als236.pdf SN74ALS236]
第2,096行： 第2,099行：
 
| 8个 buffer, inverting outputs
 
| 8个 buffer, inverting outputs
 
| Schmitt trigger
 
| Schmitt trigger
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [http://www.ti.com/lit/gpn/sn54ls240 SN74LS240]
 
| [http://www.ti.com/lit/gpn/sn54ls240 SN74LS240]
第2,104行： 第2,107行：
 
| 8个 buffer, non-inverting outputs
 
| 8个 buffer, non-inverting outputs
 
| Schmitt trigger
 
| Schmitt trigger
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [http://www.ti.com/lit/gpn/sn54ls240 SN74LS241]
 
| [http://www.ti.com/lit/gpn/sn54ls240 SN74LS241]
第2,112行： 第2,115行：
 
| 4个 bus transceiver, inverting outputs
 
| 4个 bus transceiver, inverting outputs
 
| Schmitt trigger
 
| Schmitt trigger
−
| three-state
+
| 三态逻辑
 
| 14
 
| 14
 
| [https://web.archive.org/web/20040608202058/http://focus.ti.com/lit/ds/symlink/sn74ls242.pdf SN74LS242]
 
| [https://web.archive.org/web/20040608202058/http://focus.ti.com/lit/ds/symlink/sn74ls242.pdf SN74LS242]
第2,120行： 第2,123行：
 
| 4个 bus transceiver, non-inverting outputs
 
| 4个 bus transceiver, non-inverting outputs
 
| Schmitt trigger
 
| Schmitt trigger
−
| three-state
+
| 三态逻辑
 
| 14
 
| 14
 
| [http://www.ti.com/lit/gpn/sn74ls243 SN74LS243]
 
| [http://www.ti.com/lit/gpn/sn74ls243 SN74LS243]
第2,128行： 第2,131行：
 
| 8个 buffer, non-inverting outputs
 
| 8个 buffer, non-inverting outputs
 
| Schmitt trigger
 
| Schmitt trigger
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [http://www.ti.com/lit/gpn/sn54ls240 SN74LS244]
 
| [http://www.ti.com/lit/gpn/sn54ls240 SN74LS244]
第2,136行： 第2,139行：
 
| 8个 bus transceiver, non-inverting outputs
 
| 8个 bus transceiver, non-inverting outputs
 
| Schmitt trigger
 
| Schmitt trigger
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [http://www.ti.com/lit/gpn/sn74ls245 SN74LS245]
 
| [http://www.ti.com/lit/gpn/sn74ls245 SN74LS245]
第2,176行： 第2,179行：
 
| 1 of 16 data selector/multiplexer
 
| 1 of 16 data selector/multiplexer
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 24
 
| 24
 
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n273 SN74AS250]
 
| [https://archive.org/details/bitsavers_tidataBookVol3_25840031/page/n273 SN74AS250]
第2,184行： 第2,187行：
 
| 8-line to 1-line data selector/multiplexer, complementary outputs
 
| 8-line to 1-line data selector/multiplexer, complementary outputs
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn74ls251 SN74251]
 
| [http://www.ti.com/lit/gpn/sn74ls251 SN74251]
第2,192行： 第2,195行：
 
| 2个 4-line to 1-line data selector/multiplexer
 
| 2个 4-line to 1-line data selector/multiplexer
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn74ls253 SN74LS253]
 
| [http://www.ti.com/lit/gpn/sn74ls253 SN74LS253]
第2,200行： 第2,203行：
 
| 2个 2-to-4 line decoder/demultiplexer, inverting outputs
 
| 2个 2-to-4 line decoder/demultiplexer, inverting outputs
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_icMaster19_198675341/page/n315 74LS255]
 
| [https://archive.org/details/bitsavers_icMaster19_198675341/page/n315 74LS255]
第2,216行： 第2,219行：
 
| 4个 2-line to 1-line data selector/multiplexer, non-inverting outputs
 
| 4个 2-line to 1-line data selector/multiplexer, non-inverting outputs
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn74ls257b SN74LS257B]
 
| [http://www.ti.com/lit/gpn/sn74ls257b SN74LS257B]
第2,224行： 第2,227行：
 
| 4个 2-line to 1-line data selector/multiplexer, inverting outputs
 
| 4个 2-line to 1-line data selector/multiplexer, inverting outputs
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn74ls257b SN74LS258B]
 
| [http://www.ti.com/lit/gpn/sn74ls257b SN74LS258B]
第2,256行： 第2,259行：
 
| 5760-bit ROM ([[Teletext]] character set, 128 characters 5x9)
 
| 5760-bit ROM ([[Teletext]] character set, 128 characters 5x9)
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0044628.pdf SN74S262N]
 
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-112/DSAP0044628.pdf SN74S262N]
第2,288行： 第2,291行：
 
| 6个 D-type latches, common output control, common enable
 
| 6个 D-type latches, common output control, common enable
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n935 SN74S268]
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n935 SN74S268]
第2,328行： 第2,331行：
 
| 4-bit by 4-bit binary multiplier
 
| 4-bit by 4-bit binary multiplier
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n647 SN74S274]
 
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n647 SN74S274]
第2,336行： 第2,339行：
 
| 7-bit slice [[Wallace tree]]
 
| 7-bit slice [[Wallace tree]]
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n647 SN74S275]
 
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n647 SN74S275]
第2,424行： 第2,427行：
 
| 1024-bit [[programmable read-only memory|PROM]] (256x4)
 
| 1024-bit [[programmable read-only memory|PROM]] (256x4)
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S287]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S287]
第2,432行： 第2,435行：
 
| 256-bit [[programmable read-only memory|PROM]] (32x8)
 
| 256-bit [[programmable read-only memory|PROM]] (32x8)
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S288]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n173 SN74S288]
第2,480行： 第2,483行：
 
| 4-bit bidirectional shift register
 
| 4-bit bidirectional shift register
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 14
 
| 14
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n989 SN74LS295B]
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n989 SN74LS295B]
第2,504行： 第2,507行：
 
| 8-bit bidirectional universal shift/storage register
 
| 8-bit bidirectional universal shift/storage register
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [http://www.ti.com/lit/gpn/sn74ls299 SN74LS299]
 
| [http://www.ti.com/lit/gpn/sn74ls299 SN74LS299]
第2,571行： 第2,574行：
 
| 8个 buffer, inverting
 
| 8个 buffer, inverting
 
| Schmitt trigger
 
| Schmitt trigger
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n315 SN74LS310]
 
| [https://archive.org/stream/MonolithicMemories-MMI-BipolarLSI1982DatabookOCR#page/n315 SN74LS310]
第2,667行： 第2,670行：
 
| 8-bit shift register, sign extend
 
| 8-bit shift register, sign extend
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1013 SN74LS322A]
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1013 SN74LS322A]
第2,675行： 第2,678行：
 
| 8-bit bidirectional universal shift/storage register, synchronous clear
 
| 8-bit bidirectional universal shift/storage register, synchronous clear
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [http://www.ti.com/lit/gpn/sn54ls323 SN74LS323]
 
| [http://www.ti.com/lit/gpn/sn54ls323 SN74LS323]
第2,715行： 第2,718行：
 
| [[programmable logic array|PLA]] (12 inputs, 50 terms, 6 outputs)
 
| [[programmable logic array|PLA]] (12 inputs, 50 terms, 6 outputs)
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n231 SN74S330]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n231 SN74S330]
第2,731行： 第2,734行：
 
| [[programmable logic array|PLA]] (12 inputs, 32 terms, 6 outputs, 4 state registers)
 
| [[programmable logic array|PLA]] (12 inputs, 32 terms, 6 outputs, 4 state registers)
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 24
 
| 24
 
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036733.pdf SN74LS333]
 
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036733.pdf SN74LS333]
第2,739行： 第2,742行：
 
| [[programmable logic array|PLA]] (12 inputs, 32 terms, 6 outputs)
 
| [[programmable logic array|PLA]] (12 inputs, 32 terms, 6 outputs)
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 24
 
| 24
 
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036733.pdf SN74LS334]
 
| [https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-111/DSAP0036733.pdf SN74LS334]
第2,763行： 第2,766行：
 
| clock driver
 
| clock driver
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n485 SN74ABT337]
 
| [https://archive.org/details/TexasInstruments-TI-Data-AdvancedLogicandBusInterfaceLogic1991OCR/page/n485 SN74ABT337]
第2,771行： 第2,774行：
 
| 8个 buffer, inverting outputs
 
| 8个 buffer, inverting outputs
 
| Schmitt trigger
 
| Schmitt trigger
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S340]
 
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S340]
第2,779行： 第2,782行：
 
| 8个 buffer, non-inverting outputs
 
| 8个 buffer, non-inverting outputs
 
| Schmitt trigger
 
| Schmitt trigger
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S341]
 
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S341]
第2,787行： 第2,790行：
 
| 8个 buffer, non-inverting outputs
 
| 8个 buffer, non-inverting outputs
 
| Schmitt trigger
 
| Schmitt trigger
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S344]
 
| [https://archive.org/details/bitsavers_tidataBookForDesignEngineers2ed_29954976/page/n_Engineers_2ed#page/n701 SN74S344]
第2,803行： 第2,806行：
 
| 8 to 3-line priority encoder
 
| 8 to 3-line priority encoder
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn74ls348 SN74LS348]
 
| [http://www.ti.com/lit/gpn/sn74ls348 SN74LS348]
第2,811行： 第2,814行：
 
| 4-bit shifter
 
| 4-bit shifter
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1035 SN74S350]
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1035 SN74S350]
第2,819行： 第2,822行：
 
| 2个 8-line to 1-line data selectors/multiplexers, 4 common data inputs
 
| 2个 8-line to 1-line data selectors/multiplexers, 4 common data inputs
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1041 SN74351]
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1041 SN74351]
第2,835行： 第2,838行：
 
| 2个 4-line to 1-line data selectors/multiplexers, inverting outputs
 
| 2个 4-line to 1-line data selectors/multiplexers, inverting outputs
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1047 SN74LS353]
 
| [https://archive.org/details/bitsavers_tidataBookVol2_45945352/page/n1047 SN74LS353]
第2,843行： 第2,846行：
 
| 8-line to 1-line data selector/multiplexer, transparent registers
 
| 8-line to 1-line data selector/multiplexer, transparent registers
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [http://www.ti.com/lit/gpn/cd54hc354 CD74HC354]
 
| [http://www.ti.com/lit/gpn/cd54hc354 CD74HC354]
第2,859行： 第2,862行：
 
| 8-line to 1-line data selector/multiplexer, edge-triggered registers
 
| 8-line to 1-line data selector/multiplexer, edge-triggered registers
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [http://www.ti.com/lit/gpn/cd74hct356 CD74HCT356]
 
| [http://www.ti.com/lit/gpn/cd74hct356 CD74HCT356]
第2,891行： 第2,894行：
 
| 8个 transparent latch
 
| 8个 transparent latch
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n465 SN74LS363]
 
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n465 SN74LS363]
第2,899行： 第2,902行：
 
| 8个 edge-triggered D-type register
 
| 8个 edge-triggered D-type register
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n465 SN74LS364]
 
| [https://archive.org/details/bitsavers_tidataBook2ed07_23301973/page/n465 SN74LS364]
第2,907行： 第2,910行：
 
| 6个 buffer, non-inverting outputs
 
| 6个 buffer, non-inverting outputs
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn54ls366a SN74LS365A]
 
| [http://www.ti.com/lit/gpn/sn54ls366a SN74LS365A]
第2,915行： 第2,918行：
 
| 6个 buffer, inverting outputs
 
| 6个 buffer, inverting outputs
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [http://www.ti.com/lit/ds/symlink/sn54hc366.pdf SN74HC366]
 
| [http://www.ti.com/lit/ds/symlink/sn54hc366.pdf SN74HC366]
第2,923行： 第2,926行：
 
| 6个 buffer, non-inverting outputs
 
| 6个 buffer, non-inverting outputs
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn54ls366a SN74LS367A]
 
| [http://www.ti.com/lit/gpn/sn54ls366a SN74LS367A]
第2,931行： 第2,934行：
 
| 6个 buffer, inverting outputs
 
| 6个 buffer, inverting outputs
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [http://www.ti.com/lit/gpn/sn54ls366a SN74LS368A]
 
| [http://www.ti.com/lit/gpn/sn54ls366a SN74LS368A]
第2,939行： 第2,942行：
 
| 2048-bit [[read-only memory|ROM]] (512x4)
 
| 2048-bit [[read-only memory|ROM]] (512x4)
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 16
 
| 16
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74S370]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74S370]
第2,947行： 第2,950行：
 
| 2048-bit [[read-only memory|ROM]] (256x8)
 
| 2048-bit [[read-only memory|ROM]] (256x8)
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74S371]
 
| [https://archive.org/details/bitsavers_tidataBookcomputerComponentsDataBook_16851665/page/nents_Data_Book#page/n181 SN74S371]
第2,955行： 第2,958行：
 
| 8个 transparent latch
 
| 8个 transparent latch
 
|
 
|
−
| three-state
+
| 三态逻辑
 
| 20
 
| 20
 
| [http://www.ti.com/lit/gpn/sn54ls373 SN74LS373]
 
| [http://www.ti.com/lit/gpn/sn54ls373 SN74LS373]